1. Field of the Invention
This invention relates to semiconductor memory and, more particularly, to a memory that appears to digital subsystems external to the memory as a dual port memory yet all accesses to the memory array occur through a single port using a synchronizer and sequencer to properly time accesses that occur at finer timing granularity using a high speed sampling clock.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art or conventional by virtue of their inclusion within this section.
Most computing systems consist of four functional blocks: a microprocessor (or CPU), memory, input/output (I/O) interface, and an I/O device. The microprocessor is typically interconnected to the memory and the I/O interface via an address bus, data bus, and control lines. The address bus provides a path in which the microprocessor can select certain storage locations in which data is stored. The data bus provides a path over which data is transferred between the microprocessor, memory, and the I/O interface.
Memory to which the microprocessor is coupled is typically referred to as semiconductor memory. Semiconductor memory, as opposed to disk storage devices such as magnetic disks, optical disks, and magneto-optical disks, are coupled closer to the microprocessor and can read data and write data faster than the magnetic or optical heads typically associated with disk storage devices.
The major forms of semiconductor memory include random access memory (DRAM and SRAM), non-volatile programmable memory (PROM, EEPROM, and EPROM), and read-only memory (ROM). The various forms of semiconductor memory involve storage cells arranged in multiple rows and columns, which form an array. Writing to or reading from the array in random fashion is referred to as accessing a random access memory or RAM. While DRAMs enjoy a denser array of cells, SRAMs can be written to and read from (i.e., accessed) faster than DRAMs.
There may be instances in which two or more microprocessors or other such electronic subsystems present addresses and data to the semiconductor memory at the same time or at different times. The electronic subsystems and semiconductor memory can operate at the same clock rate and thus synchronous to each other, or at different clock rates and thus asynchronous to each other. If, for example, two digital subsystems share the same semiconductor memory, such as RAM, each subsystem can access the RAM half the time, assuming the subsystems are clocked synchronous to each other. The limitation of a subsystem accessing the semiconductor memory on every other cycle becomes problematic given the difficulties with interleaving transactions between subsystems. Resulting there from, dual-port or multi-port RAMs became popular. For example, dual-port RAMs do not generally have restrictions regarding accesses between the two ports, and each subsystem can be operating at different clock rates (i.e., asynchronous to each other).
Multi-port memory allows each subsystem access to the array through its dedicated port. Address, data, and control signals from that subsystem arrive at the dedicated port for each subsystem to allow two or more subsystems access to the array at the same time. A problem occurs, however, whenever two or more subsystems access the same addressable location at the same time and, specifically, whenever those accesses involve a write operation. For example, if a first subsystem attempts a write access to the same location as a second subsystem, then a conflict can occur. The same is true if a first subsystem attempts a write access and a second subsystem attempts a read access to the same location. Proper timing of the multiple write accesses or multiple read/write accesses must be determined, and a convention set to guarantee data integrity. While multi-port memories beneficially offer simultaneous access to different portions of memory or read accesses to the same portion, multi-port memories remain restrictive when a read/write or write/write access occurs to the same memory location.
It would be desirable to maintain some of the operational efficiencies of a dual-port or multi-port memory. It would be further desirable to implement the multi-port operational efficiencies within an array of storage cells that are accessed from only a single port. An additional benefit of using a single-port array with the operational characteristics of a multi-port array is further compounded if the improved single-port array can perform address decoding concurrent with the staging of accesses to the array. Staging those accesses can desirably occur by determining time differences between transitions of clocking signals which form the corresponding accesses, and then performing the accesses based on those time differences or according to a predetermined convention or rule if the clock differences are substantially zero.